Heterogeneous Advanced Cache and Memory Architectures for Emerging Applications and Systems

PI: Dr. Mainak Chaudhuri

Traditional microprocessor caches are designed with static random access memory (SRAM) technology. However, growing such caches in capacity leads to high chip area overhead. Dynamic random access memory (DRAM) technology, on the other hand, offers high density at the expense of slow access latency. The increasing memory footprints of the important existing and emerging applications such as databases, web servers, photo-realistic animation, and large-scale scientific computing simulations have motivated the microprocessor industry to look into heterogeneous cache hierarchies that are built with SRAM as well as DRAM technologies.

This project squarely focuses on the design challenges of such cache hierarchies. Specifically, we explore the design of DRAM caches along several different dimensions such as optimal utilization of DRAM cache pages, replacement algorithms in DRAM caches, prefetching and scrubbing mechanisms in DRAM caches, etc. When a DRAM cache level is added to a traditional SRAM cache hierarchy, interesting optimization problems arise. One such problem is to compute the optimal placement of data in these two parts of the hierarchy so that both latency and delivered bandwidth are optimized. This research effort is done in collaboration with the Intel architecture group.